Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing

一种利用服务器主板bmc和cpld交互快速诊断主板时序的方法

Abstract

本发明提供一种利用服务器主板BMC和CPLD交互快速诊断主板时序的方法,涉及服务器设备领域,本发明利用CPLD(FPGA)可定制的引脚和内部寄存器的特点,在现有主板的CPLD(FPGA)外部增加一条通信总线用于和BMC通信,内部增加寄CPLD(FPGA)用于记录主板时序状态。在不增加主板硬件的情况下实现了对主板时序状态的监控和记录。
The invention provides a method for using interaction of a server motherboard BMC (baseboard management controller) and CPLD (complex programmable logic device) for rapid diagnosis of motherboard timing and relates to the field of server equipment. Through the use of the characteristics of customizable pins and internal registers of CPLD (FPGA-field programmable gate array), a communication bus is externally added on an existing motherboard CPLD (FPGA) to be used for communicating with BMC, and CPLD (FPGA) is internally added to record a timing state of the motherboard. Monitor and record of the timing state of the motherboard are realized with no motherboard hardware to be added.

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