Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing



The invention provides a method for using interaction of a server motherboard BMC (baseboard management controller) and CPLD (complex programmable logic device) for rapid diagnosis of motherboard timing and relates to the field of server equipment. Through the use of the characteristics of customizable pins and internal registers of CPLD (FPGA-field programmable gate array), a communication bus is externally added on an existing motherboard CPLD (FPGA) to be used for communicating with BMC, and CPLD (FPGA) is internally added to record a timing state of the motherboard. Monitor and record of the timing state of the motherboard are realized with no motherboard hardware to be added.




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